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January 2026 Brown Bag Webinar Recap

The Footprint of Semiconductor Chip Manufacturing


Overview

How can life cycle thinking help the semiconductor industry understand and reduce the environmental footprint of chip manufacturing?

In this January Brown Bag session, Cédric Rolin, Manager of imec’s Sustainable Semiconductor Technologies and Systems (SSTS) Program, examined the environmental impacts of integrated circuit (IC) manufacturing and why chip production represents one of the largest contributors to the embodied climate footprint of digital technologies. Drawing on insights from imec’s imec.netzero model, the talk highlighted how the complexity of semiconductor fabrication –energy-intensive tools, high-GWP process gases, high-purity materials, and extensive infrastructure — drives substantial impacts long before chips are integrated into final products.

The discussion also explored how bottom-up life cycle assessment can reveal environmental hotspots within fabs, support more transparent decision-making, and inform strategies to decarbonize a rapidly growing industry facing increasing demand from AI, data centers, and advanced electronics.

Key Themes from Webinar

  • Manufacturing dominates chip impacts: For chips used in consumer goods such as smartphone and laptops, the majority of a chip’s climate footprint occurs during manufacturing, often exceeding impacts from use or end-of-life phases due to the extreme complexity and precision required in fabrication. The picture is different for chips used in high-usage intensity applications such as data centers where operational emissions can be higher than embodied emissions, depending on the carbon intensity of electricity supply.

  • Energy and process gases as major hotspots: Electricity consumption and high-GWP fluorinated process gases — particularly in etching steps — are among the largest contributors to fab-level emissions, with outcomes strongly influenced by electricity grid mix and abatement performance.

  • Materials and upstream supply chains matter: High-purity materials, especially silicon wafers and specialty chemicals, contribute meaningful scope 3 impacts, highlighting the importance of supply-chain transparency and material efficiency.

  • Growth and rebound effects: Rapid expansion of semiconductor manufacturing capacity — driven by global investment and AI-related demand — poses challenges for absolute emissions reductions, even as efficiency improves.

  • Bottom-up LCA for actionable insight: imec’s imec.netzero model enables granular, bottom-up life cycle assessment of chip manufacturing, helping identify process-level hotspots and evaluate mitigation strategies across current and future technology nodes.

  • Environmental scoring to guide innovation: The emerging use of environmental scoring (E-score) aims to complement traditional performance, power, area, and cost metrics, embedding life cycle thinking directly into R&D and process design decisions.

  • Life cycle thinking beyond climate alone: Addressing sustainability in semiconductor manufacturing requires consideration of multiple impact categories —including water use, resource depletion, and novel entities — while avoiding solutions that shift burdens elsewhere.

About the Speaker

Cédric Rolin is manager for imec’s Sustainable Semiconductor Technologies and Systems (SSTS) Program. He holds both an M.S. and a Ph.D. in materials science from Université Catholique de Louvain and spent 15 years advancing research in flexible electronics and nanoimprint lithography at imec and the University of Michigan. Over the past four years, Cédric has focused on driving sustainability in the semiconductor industry, with a particular emphasis on assessing and reducing the environmental footprint of manufacturing processes.

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Continue the Conversation

EarthShift Global’s Brown Bag Webinar Series brings together sustainability leaders from industry and academia to share methods, tools, and insights that advance life cycle thinking. Explore our upcoming sessions and past recordings here.


Edited Webinar Transcript: (Sectioned with Timestamps)

0:00 — Welcome + Speaker Intro (Tess)

Hello everybody and welcome to our first Brown Bag Webinar of 2026.
My name is Tess Konnovitch and I’m the Scientific Marketing Manager here at EarthShift Global, and I want to thank you all for joining us today. We’re excited to host today’s webinar, The Footprint of Semiconductor Chip Manufacturing.

Our speaker today is Cédric Rolin, Manager for imec’s Sustainable Semiconductor Technologies and Systems program. He holds both a MS and a PhD in materials science from Université Catholique de Louvain and spent 15 years advancing research in flexible electronics and nanoimprint lithography at imec and the University of Michigan. Over the past four years, Cédric has focused on driving sustainability in the semiconductor industry with a particular emphasis on assessing and reducing the environmental footprint of manufacturing processes.

We’re so excited for your talk, and we’ll be hosting a Q&A session at the end of this talk. So, our audience, if you can put all of your questions during the session in that Q&A feature, I will be reading them aloud at the end of this session.

So without further ado, I’m going to hand it off to Cédric. Thank you for being here, and I’m excited to learn from you.

1:18  — Talk outline + what imec is (Cédric)

Thanks a lot, Tess. Let me get started.

This is the outline of the talk, and those are the topics I will discuss today. First I will address what are the areas of concerns from the semiconductor industry, and then I will take a dive into the imec.netzero model for integrated circuit chip manufacturing. I will also discuss the topic of environmental scoring as a way to guide innovation, and then I will conclude.

Before starting with the first topic on the menu, I just wanted to give a quick introduction of what imec is. imec is a research center specialized in semiconductor technologies, and it has existed for 40 years now and has been playing a pioneering role in the development of semiconductor technologies.

Today, in 2025, imec has more than 6,000 employees of more than 100 nationalities. The headquarters of imec is based in Leuven, close to Brussels in Belgium. You can see here a picture of the campus where we are working, that contains multiple fabs with a total of 12,000 square meters of R&D infrastructure: clean rooms with more than 250 tools, including 200 and especially 300 mm tools operating around the clock.

We are essentially the biggest semiconductor R&D lab out there, and we are working with pretty much all the companies across the semiconductor supply chain. Within imec we have multiple programs developing multiple types of technologies, including future technologies that will come on the market in 10 to 15 years.

I’m the program manager for the SSTS program: Sustainable Semiconductor Technologies and Systems. That program has a focus on sustainability, where the core mission is to help the semiconductor or IC manufacturing value chain reach its environmental sustainability target. In the program we have 28 company partners, including big system companies, big fabless companies, fabs and foundries, material suppliers, and equipment manufacturers supplying to the foundries. We also interact with government for public funding, industry associations, academia, and other research and technology organizations.

4:35 – Areas of concern in the semiconductor industry (Cédric)

Now moving to the first item of the menu: what are the areas of concerns for the semiconductor industry.

The first thing I wanted to flag is that our industry is really complex. We are producing some of the most complex mass-produced objects.

To take a quick look at the life cycle of making a chip: electronics companies put products on the market and specify what the chip should do. Then it moves to design, where engineers specify what type of chip is needed. The design is pushed into a semiconductor foundry to fabricate the chip. The wafer, after testing, will be cut into a number of dies. The chips will be picked out and assembled into packaging, and then the packaged chip moves into the maker of the final product and is assembled into a product to come into the market.

If we zoom in into the semiconductor foundry: semiconductor foundries realize a technology where you need to repeat a number of process steps. Those process steps typically include deposition of a thin film, a lithography step where we put a resin and exposure and then develop the resin to punch holes, then a dry etch to dig into the deposited layer, and then cleaning. This sequence is repeated 40 to 100 times, and every step needs to be aligned with the previous one to create the technology. There are many process steps needed to realize circuitry on top of a silicon wafer.

This industry is growing fast. Those projections are from two years ago, so probably the projections are even stronger today. Between 2020 and 2030, the industry was projected to almost double in 10 years. Many 300 mm fabs are coming online today, and more are coming. A lot of this growth has been fueled by massive funding after the COVID period, with chip acts in the US and Europe. Japan has massively funded its industry, India as well. A lot of money has been invested to increase chip production capacity.

Moving to areas of concern, I wanted to take the planetary boundaries picture to place things in perspective. There are nine planetary boundaries. Climate change is one, but we have other boundaries that have been crossed: for example, biodiversity, novel entities (related to plastic pollution or PFAS, for example).

When it comes to climate change, we know the planet is warming up. From a semiconductor industry perspective: if we have anthropogenic emissions worldwide of about 36 gigatons, the total weight of the ICT industry is about 1.2 gigatons, and that number is fast increasing especially with the advent of generative AI technologies. Within the footprint of ICT, making the chips has been estimated in 2023 to be 175 million tons, just to manufacture the chips, plus downstream steps and the use phase consumption.

On novel entities, our industry uses a lot of different materials and releases some in the waste stream. One issue is PFAS: a large class of materials involving fluorine chemistry. There is a need to reduce the usage of PFAS and reduce the release of PFAS.

Another area of concern is resource use. The industry uses a lot of materials across the periodic table, some under threat in terms of availability or sustainability. The industry uses high purity material and can face issues with resource depletion or geopolitical tension.

Another concern is water. This map shows expansion of the semiconductor industry in areas where water scarcity can be a problem. Foundries consume quite some water to make a chip.

These sustainability problems have been recognized, especially climate change, and multiple companies across the board have made commitments. You can see Apple unveiling the first carbon neutral product, TSMC accelerating the switch to renewable energy adoption, and suppliers like ASM making commitments to reduce impacts.

This is a report published by the semiconductor industry consortium in 2024 about decarbonization, trying to establish a roadmap and understand where the industry is going. The ideal trajectory respects the Paris agreement. Business-as-usual has been computed as a top trajectory where, by 2050, the industry would produce 168 megatons for scope 1 and scope 2 only (no scope 3). Taking into account all the pledges across the industry, there would be a faster decarbonization trajectory with a peak reached in 2030 before progressive decarbonization reaching a total of 60 megatons in 2050.

This data was computed before the generative AI boom, which may slightly change the picture as demand for chips may further increase.

15:05 — imec.netzero model + hotspots in chip manufacturing impacts (Cédric)

Now moving on to what we are doing in the SSTS program at imec: modeling the environmental impact of integrated circuit chip manufacturing. The model is named imec.netzero. It’s both the name of the model and the name of the web app that embeds the model and enables it. There is a version publicly accessible via https://netzero.imec-int.com. If you make an account, it is possible to get access to some of the data I show.

We launched this exercise about five years ago to get a better picture of the climate impact of making chips. In a paper in 2021, it was shown that about three quarters of Apple’s footprint is related to making their products, and about half of that is related to manufacturing integrated circuits. Another independent paper on a generic smartphone shows about 70% of the total climate impact is related to production of the object, and about 38% of the total is related to manufacturing the chips inside the smartphone. In those types of consumer goods, it accounts for the largest share of climate impact and dominates over product use phase.

To compute climate impact data, you can look into scientific literature, LCA databases like GaBi, and reporting from companies. But there is a lot of scattering due to different scopes, sources, and approaches. Company reporting is often top-down and aggregated, not given per chip or per node, and methodology is not clear. So it’s difficult to find your way.

When we started, we wanted to provide quality transparent data on environmental impact and model generic high volume manufacturing plants. This is how imec.netzero was created: a virtual fab model for environmental impact assessment enabling a bottom-up life cycle assessment. The analysis can identify high impact problems, hotspots, and look into future technologies.

We use life cycle assessment: goal and scope, inventory phase, impact assessment, and interpretation.

Applied to a virtual fab model: we look into high volume manufacturing of multiple integrated circuit technologies (logic, memory, RF, imagers, photonics, packaging). Results are expressed per wafer (kg CO2e per wafer) and can be functionalized (per square cm). We characterize multiple impact categories (climate change, resource depletion, water usage).

System boundaries: we study everything inside a fab as the foreground where we collect primary data. We also have the background to get cradle-to-gate silicon sheet manufacturing, representing the supply chain.

How we compute the data at a high level: we gather process-level data on tools (electricity, water use, nitrogen, cooling, compressed air) and process data (gas consumption, waste). We build process flows like a cooking recipe. For advanced technologies we are talking about 1,500 process steps. We also need fab modeling: facilities, abatement, water handling, yield, wafer movement—like kitchenware. Combine these to come up with an inventory (energy and materials per wafer), then do impact analysis using characterization factors (e.g., GWP).

Because results are bottom-up, they have high granularity. We can identify high impact steps, do sensitivity analysis, and run future process flows.

An oversimplified way: tool time × electrical power gives electrical energy; then use electricity carbon intensity to convert kWh to CO2e. For gases: tool time × gas flow gives volume; some gas is consumed; non-consumed goes through abatement; the part not destroyed is converted via GWP to CO2e.

The full methodology is available on the public version.

Results across logic nodes show increasing complexity (more and more process steps) and increasing total carbon footprint per wafer as we move to more advanced nodes. There was a dip around 7 nm with the introduction of EUV, which saves process steps. Other technologies: DRAM, 3D NAND, RF. 3D NAND can have a massive footprint per wafer.

If we convert per litho mask per square cm, emissions are more stable across many technologies except 3D NAND, because you do less lithography to pattern the full active stack.

If we zoom into what’s going on in a fab, we can split results by process area and by subfab contributors (incoming material, power, chillers, process gas emissions, ultrapure water).

Hotspots:

  • Tool electrical energy: tools consume a lot of power; fabs consume a lot of power. There is a high dependence on electricity mix (average ~500 g CO2e/kWh vs clean grids below 100). Taiwan electricity is not very decarbonated.

  • Process gas emissions: fluorinated gases with high GWP, mainly related to Dry Etch Process Area. Abatement exists with destruction removal efficiency up to 95–99%, but older fabs may not be well equipped. Modeling shows biggest final emissions after abatement include CF4 and SF6.

  • Upstream materials: scope 3 material supply, about 15% of total, with silicon wafer supply being a big component. Semiconductor fabs have a bill of materials around 150 to 200 materials with high purity requirements and a vast supply chain.

  • Cooling: lots of heat generated; removed by chillers and cooling water systems; consumes energy and water. Cooling towers remove heat through evaporation. Chillers often use fluorinated heat transfer fluids, which have high GWP and are PFAS, connecting back to novel entities.

Addressing hotspots: there are many research topics and options. A marginal abatement cost curve approach can help prioritize. In the Micron example: process optimization and improved tool efficiency are big win-wins; energy efficiency upgrades, leak reduction, waste recovery. Other measures have costs: gas abatement, waste treatment, renewable electricity, electrification. Solutions include decarbonization of electricity supply and supply chain, full abatement deployment, material replacement, process optimization, facilities optimization, R&D. Economic viability and return on investment is a key driver.

Important context: the industry is complex and risk-averse due to yield and high confidentiality. R&D horizon is long and impacts future technologies. Regulation is important. It’s important not to solve one problem while creating another; life cycle thinking is needed beyond a purely climate-centric view.

46:20 — Environmental scoring (E-score / Ecore) + conclusion (Cédric)

Before closing, I want to say a word about environmental scoring as a way to guide innovation. We call that E-score (environmental score). With limited resources we can’t solve all challenges. Environmental concern should become the concern of all R&D engineers innovating tomorrow’s technologies. We want an environmental metric to complete the PPAC scorecard (performance, power, area, cost). We want to add an E, but we need the right metric: how to measure environmental impact in a way engineers can understand, with a user-friendly platform and dissemination.

The E-score methodology is based on imec.netzero, but instead of a full technology, the idea is to do it at a process-step level: a mini LCA on a single process step. Use imec.netzero to establish the inventory, and rely on Environmental Footprint 3.1 for impact analysis. The methodology goes from inventory to characterization across 16 EF 3.1 impacts, then normalization and weighting to compute a single score.

If we only report a single score, it might not be speaking to process engineers, so the proposal is to report the final E-score plus inventory values (electricity usage, water, materials consumed, waste generated) and impact values, with standardized plots for comparison of reference vs test processes.

E-score is work in progress. We are testing it with process and integration engineers at imec to find the best way to calculate and communicate the data. The goal is a standardized dashboard that allows understandable comparisons and portability across institutions.

To conclude, key take-home messages:

  • Climate change impact of IC chip manufacturing is expected to increase in the future; the industry needs to work hard to fulfill pledges and achieve net zero by 2050.

  • IC chip manufacturing is one of the largest contributors to the carbon footprint of ICT devices due to complexity and ultra low entropy manufacturing across a complex value chain. Carbon footprint per mass is extremely high, on par with gold, because it consumes massive electricity and high purity materials.

  • Climate change impact can be reduced by effective abatement of high-GWP process gases, use of renewable / non-fossil electricity, defossilizing the supply chain, and adopting environmental scoring early in technology design to steer innovation.

Acknowledgements to colleagues, program partners, and European funding projects including Genesis.

54:30 – Q&A

Q1: Question number one is: chip manufacturing getting more intensive per centimeter squared?

Cédric: If we use a functional unit that would be kilogram CO2 equivalent per square cm, the answer is yes. Certainly. It’s always a complex question because we cannot just divide by the area of the wafer. The wafer is going to be cut to recuperate a certain amount of dies. Some of those dies are going to yield and some are not. Generally speaking, the bigger the die—if you make a very large chip—the yield is getting worse. The kilogram CO2 equivalent per square cm is going to increase across generations.

So definitely the footprint per square cm for 2 nanometer technologies is larger than for 90 nanometer, because there’s more processing done to create the same area of wafer.

Chip size also plays a role. If you take a single technology like 2 nanometer and make a 1×1 mm chip, then 10×10 mm, then 26×33 mm, the yield will be worse on the bigger one, meaning the kilogram CO2 equivalent will be higher on those bigger chips because the yield is worse. It’s a dual question: it increases due to technology complexity, but chip size also plays a role.

Today, as the industry is moving towards GPUs—using pretty large chips of complex technology—those chips have a very high impact. The hope is that with chiplet technologies, where you can combine multiple smaller chips with better yield and better functionalization, you can revert that trend and better use the silicon.

 

Q2: Do you have a timeline for including the EF 3.1 impact categories in output?

Cédric: The 16 EF 3.1 impact categories are available in imec.netzero for the program partners. For the public version today, we don’t have an agenda on that. Maybe in the future this is something we enable. Today in the public version there’s a limited set of impact categories.


Q3: You showed imec as having both gate-to-gate and cradle-to-gate models. For any studies using the imec model in LCA studies, are the values based on gate-to-gate or cradle-to-gate?

Cédric: It’s always cradle to gate. We use the distinction to distinguish the foreground—where we use primary data—from the background—data from the supply chain. Foreground is primary data collected in imec fab and from program partners. Background typically comes from ecoinvent through standardized LCA practice. We’re not able to fully connect everything because semiconductor materials are specific, so we build the best proxies possible.

Whenever we report results, the results encompass the full cradle-to-gate analysis all the way to making of the die. We also model packaging, but packaging is not available in the public part of netzero; it is available to program partners.


Q4: Given that most manufacturing information from companies is proprietary, how have the fab models in netzero been validated?

Cédric: On the foreground, we collect data from multiple sources. We’re lucky at imec because we collaborate with pretty much every company and have access to our own R&D fab with industrial-grade equipment. We do measurement campaigns on tools to collect data, and partners share data with us.

For validation: the netzero model is audited once a year by a third party. They open the full model and provide verification and certification that the model is doing what it is supposed to do. Besides that, foundry partners provide benchmarking exercises: compare bottom-up results with top-down numbers from real fabs based on electricity use and procurement versus annual production. That has helped us calibrate. Netzero has existed about four years, and we have confidence we are reaching numbers that are generally representative of the industry.


Q5: How is this model usable for the average LCA practitioner?

Tess: How does imec envision these models becoming useful for the average LCA practitioner? The average user doesn’t have die size information, doesn’t know which fab their IC was made in, and must add a packaging model as well. The current option is to use older proxies in LCA for experts. How does imec envision supporting the LCA industry with more accurate IC and photonic product models that a typical user can actually use?

Cédric: It’s a very good question and to the point—how to make this data more actionable. There’s a gap. If your job is to calculate a product carbon footprint and there are many chips in the product, it’s very difficult to understand what’s inside those chips. You need an investigation to understand the package, technology, number of chips, size of the chip. You can do that for a single chip, but it’s hard if your product uses hundreds of chips.

We recognize that gap. Program partners have capabilities to put sufficient manpower and resources into this investigation, but that doesn’t help smaller system companies that don't have all those capabilities.

We are investigating ways to help by making data more broadly available and more user friendly, but this is work in progress in the SSTS program. Today we are helping maybe 70% of the effort; the last 30% is future work.


Q6:  Why is the infrastructure excluded? Fabs are one of the shortest lived industrial buildings.

Cédric: Very good question. In the scope exercise, you start to exclude things because you have no information. To be more rigorous, we need to estimate importance: footprint of making equipment, infrastructure, buildings, facilities, and allocate over fab lifetime.

Initial assessment showed infrastructure construction footprint is quite negligible when allocated over the lifetime, and fab closures are rare—fabs built 30 years ago are still producing today. Equipment manufacturing could be significant, but there’s a lack of data. Some equipment manufacturers are progressing to provide footprints, but we haven’t been able to insert that into the model today. Probably work for the future. It’s not easy to compute given complexity.


Q7: Curious on the sources of primary and background data used in the tool and representativeness across the industry.

Cédric: Foreground data: imec fab is R&D, not production. Production fabs have tool groups with many identical tools; imec has beta tools before production, industry-ready but unique versions. Data derived on tools is representative of what an equivalent tool looks like in production, though not fully optimized like in a fab. It’s not like measuring lab tools that are nonrepresentative.

Background data: we base characterization mostly on ecoinvent, but we do a lot of pre-engineering because chemicals are very specific. We build models to represent chemicals, then source components needed to make them. We discuss with material suppliers to supply better models, but one difficulty is models that are representative for climate change but not other impact categories, making them hard to plug into our scope. That’s one reason we fall back on LCA source data.


Q8:  Is anything being done to consider heat pumps to return the heat back to the equipment from the fab?

Cédric: There’s a lot done in this field. There are opportunities to valorize waste heat through heat pumps. In the marginal abatement cost curve, this is a win-win where you can gain money because you don’t need to spend electricity or fossil fuels to generate heat. The subfab is a place where transformations can happen; clean room floor is much harder to change once installed. Modern fabs installed today have optimized waste heat valorization pathways as well as water.

Q9: Has stochastic multi-attribute analysis, or SMAA, been considered instead of a single score?

Cédric: No, and I would love to hear more about it. The topic of the single score is endless internally. Everybody hates it for multiple reasons, and at the same time we realize we cannot throw 60 different figures to people and ask them to improve all of them. Since my title is a manager, I like clear KPIs, and I can take E-score as one KPI and tell engineers: you have to decrease that value. It can useful, it can be criticized in normalization and weighting. At the same time, if everybody agrees on the same method and language, it might be a language we can speak. I’m not familiar with the stochastic method you mentioned; I would love to learn more about it.

Tess: I will send you over some resources we have on the website.


Q10: Who is driving normalized/weighted E-score?

Cédric: One original interest came from equipment suppliers. E-score is a mini LCA at a process step level. If you run a dry etch design of experiment, for every entry you can get an environmental assessment. This is directly beneficial for equipment suppliers—they can include it in recipe development on their tools.

Another principal source of motivation today comes from public funded projects. We see partners developing “more sustainable” solutions, but what does that mean? To answer correctly, you need the right methodology. imec can supply this methodology so partners can calculate sustainability impact of their invention and research. It’s a deliverable for the FAME project and also something we work on in the Genesis project.


Q11: Any comments on recycling?

Cédric: Recycling is complex. When people think recycling, they think end-of-use products where you tear down, recuperate chips, and valorize them in a loop. E-waste is difficult to recycle. In silicon chip manufacturing we talk about nanometer quantities added on a small object that gets mixed into a heterogeneous set in the final product. To recuperate nanometer quantities of a metal from that is complicated to have a positive return on investment.

E-waste recycling is done, but mostly for a few materials such as gold used in packaging; maybe copper. Apart from that, not many metals can be efficiently and economically recycled.

Another opportunity is at the fab level: making chips generates a lot of waste—water and chemicals. Water recycling is done in fabs. There may be opportunities to recycle waste chemicals if we segregate waste early before it’s mixed. There’s more potential to recycle fab waste than e-waste.

There are technical barriers and “soft barriers” related to quality perception, responsibility, and material supplier accountability. 


Q12: Will the imec.netzero models ever be incorporated into another life cycle inventory database like ecoinvent or Sphera?

Cédric: We are thinking about it, but I cannot further comment. We do realize there would be a lot of value for the model to be more broadly available and easier to use for LCA practitioners.


Q14: Given that demand is rising and impact of newer technologies is higher and higher, do you see any pressures pushing impact down? Is this a runaway rebound effect situation?

Cédric: It’s certainly a rebound effect. I would invite the person asking to look into the work from David B., a professor at UC Louvain in Belgium—his team has been publishing on the topic. There is a rebound at play. IC chip technology is effective at answering needs, so we are consuming more and more.

Is this a runaway rebound? I am not sufficiently educated in the field to comment on that.


Q15: Has imec published any citable reports with the information presented in these slides, or are there any reports or documents you’d like to direct our audience to?

Cédric: First, look at our website. The methodology is available there with sources. We do have a few publications. The two most relevant papers were published at the IEDM conference: a paper in 2020 and a paper in 2023. The 2020 paper dates a bit, but it shows the foundation and where we started.

1:29:42 — Closing

Tess: Excellent. Thank you, Cédric. I’m going to be putting together a summary of this talk for our website and I will make sure to consult Cédric with any links and I’ll make sure to put all that together for you.

Thank you to our audience for being so engaged today. Cédric, you answered possibly a record number of questions. Thank you for your extra time. Everyone was super engaged, and I hope everyone has a really nice day and join us next month for our February Brown Bag webinar. Thank you, Cédric.

Cédric: Thank you. Thank you very much. Bye. Have a good day.

Written
Jan 30, 2026
Read time
27 min read
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LCASustainability